Integrated circuits comprise many transistors and the electrical interconnections between them. Depending upon the interconnection topology, transistors perform Boolean logic functions like AND, OR, NOT, NOR and are referred to as gates. Some fundamental anatomy of an integrated circuit will be helpful for a full understanding of the factors affecting the flexibility and difficulty to design an integrated circuit. An integrated circuit comprises layers of a semiconductor, usually silicon, with specific areas and specific layers having different concentrations of electron and hole carriers and/or insulators. The electrical conductivity of the layers and of the distinct areas within the layers is determined by the concentration of ions called dopants that are implanted into these areas. In turn, these distinct areas interact with one another to form the transistors, diodes, and other electronic devices. These devices interact with each other by electromagnetic field interactions or by direct electrical interconnections. Openings or windows are created for electrical connections through the layers by an assortment of processing techniques including masking, layering, and etching additional materials on top of the wafers. These electrical interconnections may be within the semiconductor or may lie above the semiconductor areas using a complex mesh of conductive layers, usually of metal such as aluminum, tungsten, or copper fabricated by deposition on the surface and then selectively removed. Any of these semiconductor or connectivity layers may be separated by insulative layers, e.g., silicon dioxide.
Integrated circuits and chips have become increasingly complex with the speed and capacity of chips doubling about every eighteen months because of the continuous advances in design software, fabrication technology, semiconductor materials, and chip design. An increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to design and manufacture a chip that performs as actually desired. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. These difficulties increase the expense and risk of designing and fabricating chips, especially those that are custom designed for a specific application. The demand for complex custom designed chips has increased along with the demand for applications and products incorporating microprocessors, yet the time and money required to design chips have become a bottleneck to bring these products to market. Without an assured successful outcome within a specified time, the risks have risen with the costs, and the result is that fewer organizations are willing to attempt the design and manufacture of custom chips.
More powerful specialized software electronic design automation (EDA) tools intended to design chips correctly and efficiently have been introduced to meet the challenge. As the software tools evolve, however, the tools themselves have become increasingly complex requiring extensive expertise to master and use them. Correspondingly, the costs of staffing, training, and coordinating the various aspects of chip design have also increased. One general response to this dilemma has been a call for what are termed “higher levels of abstraction,” which simply means that the logical entities with which designers work are standardized and encapsulated into “black boxes” or modules. Some of the EDA tools, however, are so complex that it is difficult to adapt them to this higher level of abstraction. Customer needs and specifications must be aligned with tools and capabilities of both designers and fabrication facilities having their own design rules, equipment, molds, recipes and standards that have myriad implications for the final work and, for best practices, must be considered early in the process.
Meanwhile, several types of chips have been developed that have modules or blocks of transistors that are partly fixed and partly programmable and/or customizable. The utility of these modular chips is determined by factors such as complexity, cost, time, and design constraints to create functional electronics from these generic blocks of transistors. Field programmable gate array (FPGA) refers to a type of logic chip that can be easily reprogrammed in the field with trivial modifications. FPGAs, however, are very large and expensive having relatively high cost per function, relatively low speed, and high power consumption. FPGAs are used primarily for prototyping integrated circuit designs and once a design is set, faster hard-wired chips are produced. Programmable gate arrays (PGAs) are also flexible in the numerous possible applications that can be achieved but not quite as flexible as the FPGAs, and require more time to modify and test. An application specific integrated circuit (ASIC) is another type of chip designed for a particular application. ASICs efficiently use power compared to FPGAs and are quite inexpensive to manufacture at high volumes. ASICs, however, are very complex to design and prototype because of their speed and quality. Application specific standard products (ASSPs) are hard-wired chips that meet a specific need but this customization is both extremely time-consuming and costly. An example of an ASSP might be a microprocessor in a heart pacemaker.
Consistent with the goal to achieve the higher levels of abstraction, a difficult optimization and construction problem is that of constructing internal memory arrays required for many distinct designs. Integrated circuits, moreover, may have either an embedded or external processor connected to various registers and memory, either or both of which may be located on or off-chip. On-chip, these registers and memories may be logically and/or physically arranged in various modules that may be read and written by the processor through memory-mapped accesses connecting the registers/memory and the processor using at least one internal bus. Today, chip designers and testers manually define the specification and address map for individual registers and internal memory, as well as separately and manually specify the register transfer logic (RTL) implementation, the verification testcases, and the firmware header file. This approach is time-consuming, tedious, and prone to errors created by manual editing. Maintaining consistency and accommodating the many minute changes is very difficult.
Because the invention herein allocates memory in an integrated chip, it may be useful to present a brief discussion of how memory is used in semiconductor products. Memories are a collection of elements having a defined and repeatable purpose; if addressable, each element of the memory can be individually accessed by an address. Memories may be configured as “read-only” in that the memory stores a value indicating, e.g., a state or status. A memory may also be a “read-write” memory meaning that the value stored in the element may be observed and modified. A memory may also be a “write-only” memory meaning that the address associated with the memory element monitors an internal change but the values cannot be observed. Writing to a memory, moreover, may store or set bits to a particular value in the memory; or writing may clear bits or values within the memory. Setting or clearing bits within a memory may further trigger a counter that may affect an operation elsewhere on the integrated circuit when a threshold value in the counter is reached.
In addition to the above capabilities, it is often convenient to specify that a memory be allocated to be a control register connected to deeper internal logic of the configurable integrated circuits. An example of a control register is the counter. As internal events occur, the counter changes values. Another specialized memory is the status register whose bits are also driven by internal events. A status register is often associated with a mask register. The combination of a status and a mask register may produce a single output bit when both an internal signal and a mask/enable bit are set. Another specialized memory is the most significant bit (MSB) register. When a combination of a mask/enable bit and a status bit are arranged in priority order the MSB register can be read to determine the offset of the most significant bit that is set and enabled. Such specialized registers are not easily implementable or testable and may be referred to as performance-enhancing registers. One of skill in the art, moreover, will recognize that the above descriptive use of memories is not intended to be all-inclusive, but rather to merely provide examples of how memories and registers are used in an integrated circuit or semiconductor product.
Multiple memory blocks or modules may be part of the complex functions embedded in cell-based logic or base transistors as custom logic. Because it is embedded, this fixed logic cannot be changed without a complete respin of the silicon device even though the specific complex function realizable by that logic may not be desired and/or used in the semiconductor product. If this is the case, the effort, development, and area of the chip was wasted because the custom logic cannot be reused.
There is thus a need in the industry to increase the reliability and the flexibility of the design process and use of addressable and internal memories after manufacture within a semiconductor product yet at the same time reduce the cost of each individual design.